This invention relates to the field of trench isolation integrated circuit processing, and more particularly, to the processing of trench isolation structures.
Trench isolation has been used in the semiconductor industry to reduce circuit topography and better isolate adjacent semiconductor devices. Various proposals have been made for improving the liner in trench isolation structures. Fahey et al. U.S. Pat. No. 5,447,884, the disclosure of which is incorporated by reference herein, discloses a nitride liner with an optional thermal oxide layer for shallow trench isolation. Kawamura et al. U.S. Pat. No. 5,189,501, Poon et al. U.S. Pat. No. 5,190,889, Takemura et al. U.S. Pat. No. 5,099,304, Freeman U.S. Pat. No. 5,206,182, Hunter et al. U.S. Pat. No. 4,631,803 and Aoki et al. U.S. Pat. No. 5,384,280, the disclosures of which are incorporated by reference herein, disclose similar structures of a silicon dioxide (thermal oxide) layer followed by a silicon nitride layer for trench isolation.
Hunter et al. U.S. Pat. No. 4,631,803 additionally discloses a second oxide layer deposited over the nitride layer and a second nitride layer deposited over the second oxide layer.
Poponiak et al. IBM Technical Disclosure Bulletin, 19, No. 3, p. 905 (August 1976), the disclosure of which is incorporated by reference herein, discloses an anodization process for producing surface films of silicon oxynitride for dielectric isolation.
A silicon nitride liner has shown to be a highly effective O.sub.2 diffusion barrier. The silicon nitride liner limits the amount of oxide that can be grown in deep trenches as well as in shallow trench structures, and as such, all but eliminates silicon crystal defects from forming within the trench capacitor array. However, there are two problems with the as-deposited silicon nitride liner. First, the as-deposited silicon nitride liner has been shown to be a source of charge-trapping which leads to unacceptable levels of junction leakage in the support circuitry. Recent studies indicate that a majority of the charge-trapping occurs at the interface of the silicon nitride liner and the deposited oxide that is used to fill the trenches. Second, the process window for the silicon nitride liner is extremely narrow. If the liner is deposited equal to or less than 4 nm in thickness, the liner is not an effective O.sub.2 diffusion barrier and defects are readily formed in the trench capacitor array. If the liner thickness is greater than 5 nm, the liner is prone to attack by the hot phosphoric acid that is used to strip the pad nitride film from the silicon surface. A divot forms in the silicon nitride liner and oxide filler which may trap polysilicon (used as part of the gate conductor), metals or foreign material. A divot is an undercutting of the trench liner and oxide filler as a result of attack of the trench line by the hot phosphoric acid. Any of the aforementioned materials may lead to electrical shorts of devices.
Accordingly, it is a purpose of the present invention to have an improved liner material that is an effective O.sub.2 diffusion barrier, is resistant to hot phosphoric and other acids (e.g., hydrofluoric acid) and shows a reduced trap density.